FEATURES1. ROM: 2K x 14 bits OTP or 1K x 14 bits TTP™ (Two Time Programmable ROM)
2. RAM: 184 x 8 bits
3. STACK: 5 Levels
4. I/O Ports: Three bit-programmable I/O ports (Max. 18 pins)
5. Two Independent Timers
. Timer0
- 8-bit timer0 with divided by 1 ~ 256 pre-scale option / counter / interrupt / stop function
. T2
- 15-bit T2 with 4 interrupt interval time options
- IDLE mode wake-up timer or used as one simple 15-bit time base
- Clock source: SXT or SIRC/2
6. Two Independent PWMs
. One 8-bit PWM0 with pre-scale / period-adjustment / buffer-reload / clear and hold function
. One 8-bit PWM1 with simple fixed frequency and duty cycle
7. One analog voltage comparator
8. Min. Operating Voltage (power on) and Speed: VDD can be lowest to 1.6V when the Fsys is 4 MHz
9. PA1 ~ PA6, PB1 ~ PB6 individual pin low level wake up
10. System Oscillation Sources (Fsys)
. Fast-clock
- FXT (Fast Crystal): 1 MHz ~ 24 MHz
- FIRC (Fast Internal RC): 8 MHz
. Slow-clock
- SXT (Slow Crystal): 32768 Hz
- SIRC (Slow Internal RC)
VDD = 5V, SIRC = 110 KHz
VDD = 3V, SIRC = 88 KHz
11. System Clock Prescaler: System Oscillation Sources can be divided by 16 / 4 / 2 / 1 as System Clock (Fsys)
12. Power Saving Operation Modes
. FAST Mode: Fast-clock keeps CPU running
. SLOW Mode: Fast-clock stops, Slow-clock keeps CPU running
. IDLE Mode: Fast-clock and CPU stop, T2 keeps running
. STOP Mode: All Clocks stop, T2 stops
13. Dual System Clock
. FIRC + SIRC
. FIRC + SXT
. FXT + SIRC
14. Reset Sources
. Power On Reset
. Watchdog Reset
. Low Voltage Reset
. External pin Reset
15. 3-Level Low Voltage Reset: 1.6V / 2.1V / 3.0V (can be disabled)
16. 2-Level Low Voltage Detect: 2.2V / 3.1V (can be disabled)
17. Enhanced Power Noise Rejection
18. Built-in Power Management circuitry
19. Operation Voltage: Low Voltage Reset Level to 5.5V
. Fsys = 4 MHz, 1.6V ~ 5.5V
. Fsys = 8 MHz, 2.1V ~ 5.5V
. Fsys = 16 MHz, 3.1V ~ 5.5V
20. Operating Temperature Range: -40℃ to +85℃
21. Interrupts
. Three External Interrupt Pins
- Two pins are falling edge triggered
- One pin is rising or falling edge triggered
. Timer0 / T2 / Comparator Interrupts
22. Watchdog Timer (WDT)
. Clocked by built-in RC oscillator with 4 adjustable Reset time options
VDD = 5V, WDT = 152 ms / 76 ms / 38 ms / 19 ms
VDD = 3V, WDT = 192 ms / 96 ms / 48 ms / 24 ms
. Watchdog timer can be disabled/enabled in Power-down mode
23. I/O Port Modes
. Pseudo-Open-Drain Output (PA2 ~ PA0)
. Open-Drain Output
. CMOS Push-Pull Output
. Schmitt Trigger Input with pull-up resistor option
24. Table Read Instruction: 14-bit ROM data lookup table
25. Support 5-wire program
26. Instruction set: 39 Instructions
27. Package Types:
. 14-pin DIP (300 mil)
. 14-pin SOP (150 mil)
. 18-pin DIP (300 mil)
. 18-pin SOP (300 mil)
. 16-pin DIP (300 mil)
. 16-pin SOP (150 mil)
. 20-pin DIP (300 mil)
. 20-pin SOP (300 mil)
28. Supported EV board on ICE
EV board: EV2774