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TM57PE40

Data Sheet
DS-TM57PE40_EV19.pdf

2018/3/14
User manual
Development Documnets
AP Notes

Development Tools
TICE59NB(已停產)
TICE99
TWR98/TWR99/TWR100/TWR100A

GENERAL DESCRIPTION
TM57PE40是一個8位元高性能OTP單片機,採用CMOS製程,具有高效能、低耗電以及
高抗雜訊能力特點。它的核心是RISC-like的架構,只需36個指令,並具備內建高低頻
RC振盪器、低電壓工作的特性、快慢鐘操作運算模式、16位捕捉定時器模塊、可靈活調
整的計時器/計數器、簡易觸模按鍵模組、最多支援28 I/O腳位的靈活使用,且提供不同
數量的腳位包裝供選擇。它強大的功能使得它可以廣泛應用在多腳位I/O控制產品,例如
傳感器信號處理、消費性產品和子系統控制等等。
BLOCK DIAGRAM


FEATURES
1. ROM: 4K x 14 bits OTP or 2K x 14 bits TTP™ (Two Time Programmable ROM)
2. RAM: 176 x 8 bits
3. STACK: 6 Levels
4. Oscillation Sources
   . Fast-clock
     - FXT (Fast Crystal): 1M~24 MHz
     - FIRC (Fast Internal RC): 2/4/8/16 MHz
     - XRC (External R, External C): 10K~3 MHz
   . Slow-clock
     - SXT (Slow Crystal): 32768 Hz
     - XRC (External R, External C): 10K~3 MHz
     - SIRC (Slow Internal RC): 168K/40K/9.8K/2.6 KHz @5V; 128K/30.3K/7.6K/2K @3V
     - TKRC (Touch Key Clock): 128K/64K/16K/4 KHz @5V, un-touched; 80K/40K/10K/2.5K @3V, un-touched
5. Dual System Clock
   . FIRC + SIRC
   . FIRC + SXT
   . FIRC + XRC
   . FIRC + TKRC
   . FXT + SIRC
   . FXT + TKRC
   . XRC + SIRC
   . XRC + TKRC
6. Power Saving Operation Mode
   . FAST Mode: Slow-clock can be disabled or enabled
   . SLOW Mode: Fast-clock stops, CPU running
   . IDLE Mode: Slow-clock running, CPU stops, Timer2 is running
   . STOP Mode: All Clocks stop, Wake-up Timer is disabled or enabled
7. Operation Voltage and Speed: VDD=1.6V @4 MHz
8. 3 Independent Timers
   . Timer0 
     - 8-bit timer divided by 1~256 pre-scaler option, Counter / Interrupt / Stop function
     - Capture – high duty or low duty (pulse width measurement) 
     - Overflow and Toggle out
   . Timer1
     - 16-bit timer with two pre-scalers, Counter / Interrupt / Stop / Clear&Hold / Set / Reload function
     - Capture – period time 
     - Overflow and Toggle out
   . Timer2
     - 15-bit timer with 4 interrupt interval time options
     - IDLE mode wake-up timer or used as one simple 15-bit timer base
     - Clock source: SXT / XRC / SIRC / TKRC
9. Interrupt
   . Three External Interrupt pins
     - 2 pins are falling edge wake-up triggered
     - 1 pin is rising or falling edge wake-up triggered
   . Timer0 / Timer1 / Timer2 / WKT (wake-up) Interrupts
. Comparator output change interrupt
10. PB[7:0] individual pin low level wake up
11. Wake-up (WKT) Timer
   . Clocked by built-in RC oscillator with 4 adjustable Interrupt times
     0.9 ms/1.8 ms/30 ms/120 ms @5V, 1 ms/2 ms/32 ms/128 ms @3V
12. Watchdog Timer 
   . Clocked by built-in RC oscillator with 4 adjustable Reset Time
     100 ms/200 ms/800 ms/1600 ms @5V, 130 ms/280 ms/1100 ms/2200 ms @3V
   . Watchdog timer can be disabled/enabled in STOP mode (WDTSLPSTP, R0Eh.5)
13. 2 Independent PWMs 
   . PWM0:  
     - 8-bit with 1~8 pre-scalers, period-adjustable / duty-adjustable / 
        Clear&Hold / Non-inverting or inverting output.
   . PWMA: 
     - 8+2 bits, duty-adjustable controlled PWM 
14. One analog voltage comparator
15. 15-channel Touch Key, supports one key wakeup for low power consumption
16. Reset Sources
   . Power On Reset / Watchdog Reset / Low Voltage Reset / External Pin Reset
17. Low Voltage Reset Option: LVR1.5V, LVR1.5V disable in SLEEP, LVR2.3V, LVR3.2V 
18. Operation Voltage: Low Voltage Reset level to 5.5V
   . fosc = 4 MHz, 1.7V ~ 5.5V
   . fosc = 8 MHz, 1.8V ~ 5.8V
   . fosc = 12 MHz, 2.1V ~ 5.5V
   . fosc = 16 MHz, 3.1V ~ 5.5V
   . fosc = 24 MHz, 4.0V ~ 5.5V
19. Operating Temperature Range: -40°C to +85°C
20. Instruction set: 36 Instructions
21. Instruction Execution Time
   . 2 oscillation clocks per instruction except branch
22. I/O ports: Maximum 29 programmable I/O pins 
   . Pseudo-Open-Drain Output
   . Open-Drain Output
   . CMOS Push-Pull Output
   . Schmitt Trigger Input with pull-up resistor option
23. Package Types:
   . 24-pin SOP (300 mil), SSOP (209 mil)
   . 28-pin DIP (300 mil), SOP (300 mil), SSOP (209mil)
   . 32-pin SOP (300 mil), QFN (4x4x0.75-0.4mm)
24. Supported EV board on ICE
    EV board: EV2787


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