FEATURES1. ROM: 4K x 16 bits Flash
With 8 table readable security keys
2. EEPROM: None
3. RAM: 256 x 8 bits
4. STACK: 8 Levels
5. System Clock type selections:
Fast clock from Internal RC (FIRC, 16 MHz)
Slow clock from Internal RC (SIRC, 95.8 KHz@25℃/VCC=5V)
- Calibrate through CFC(Capture Frequency Count)
6. System Clock Prescaler:
System Clock can be divided by 1/2/4/8 option
7. Power Saving Operation Mode
FAST Mode: Slow-clock is enabled, Fast-clock keeps CPU running
SLOW Mode: Fast-clock can be disabled or enabled, Slow-clock keeps CPU running
IDLE Mode: Fast-clock and CPU stop. Slow-clock, or Wake-up Timer keep running
STOP Mode: All clocks stop, Wake-up Timer stop
8. Independent Timers
Timer0
- 8-bit timer divided by 1~256 pre-scale option / auto-reload / counter / interrupt / stop function
Timer1
- 8-bit timer divided by 1~256 pre-scale option / auto-reload / interrupt / stop function
- Overflow and Toggle out
9. Interrupt
Timer0 / Timer1 / Wake-up Timer Interrupt
ADC Interrupt
Comparator Interrupt
PWM0/PWM1 Interrupt
LVD Interrupt
All Port Pin-change Wake-up Interrupt
CFC(Capture Frequency Count) Interrupt
10. Wake-up Timer (WKT)
Clocked by built-in RC oscillator with 4 adjustable interrupt times
- 43 ms / 86 ms / 172 ms / 343 ms @VCC=25℃/5V
11. Watchdog Timer (WDT)
Clocked by built-in RC oscillator with 4 adjustable reset times
- 175 ms / 348 ms / 1381 ms / 2761 ms @VCC=25℃/5V
Watchdog timer can be disabled / enabled in STOP mode
12. One 16-bits PWM and five 8-bits PWMs
PWM0 is 16-bits PWM with individually adjustable duties and period
PWM0 clock source: System clock (Fsys), FIRC/256, FIRC (16 MHz), FIRC*2 (32 MHz)
PWM0 supports complementary output (PWM0P, PWM0N)
PWM1~5 are 8-bits PWMs with individually adjustable duty and shared adjustable period
PWM1~5 clock source: FIRC (16 MHz) with 1/2/4/8/16/32/64/128 prescaler
PWM0N/0P/1/2/3/4/5 has two outputs
13. 12-bit ADC with 17 channels for External Pin Input and 2 channels for Internal Voltage
Two internal voltage channels: VBG, 1/4VCC
ADC reference voltage: VCC, VBG (1.183V), VBG (2.53V) , VBG (0.59V) and VBG (2V)
14. Comparator
Comparator x 1
- With 5-bit special DAC input
- DAC reference voltage: VCC or 1.183V
15. Reset Sources
Power On Reset
Watchdog Timer Reset
Low Voltage Reset
External Pin Reset
16. Low Voltage Reset (LVR) and Low Voltage Detection (LVD)
15-Level Low Voltage Reset: 1.73V ~ 3.47V, can be disabled
15-Level Low Voltage Detection: 1.9V ~ 4.31V, can be disabled
17. Operating Voltage
Fsys= 16 MHz, PWM0CKS=Fsys, LVR~5.5V. Suggest LVR ≥ 2.30V
Fsys= 8 MHz, PWM0CKS=Fsys, LVR~5.5V. Suggest LVR ≥ 1.6V
Note: Refer to the “Electrical Characteristics Graphs”.
18. Operating Temperature Range : -40°C to + 105°C
19. Table Read Instruction: 16-bit ROM data lookup table
20. Instruction set: 39 Instructions
21. I/O ports:
Maximum 18 programmable I/O pins
- Open-Drain Output
- CMOS Push-Pull Output
- Schmitt Trigger Input with pull-up / pull-down resistor option(PA7 has no pull-down resistor)
- All I/O with High-Sink except PA7
- 1/2 VCC (LCD 1/2 bias) Output (except PA7)
All pin-change wake-up (falling edge and rising edge trigger) and interrupt
22. LCD Driver
Maximum 17 software controlled COM
LCD 1/2 bias
23. Programming connectivity support 4-wire(on-board programming with power), 5-wire (ICP) or 6-wire program
24. RDCTL: Read signal delay control for Program ROM
The user must switch this bit to “4ns” to enhance the performance of minimal operating voltage
25. Trimmed VBG
Auto-selected VBG trim value by mean of ADC reference voltage selection (ADVREFS) for exact VBG.
26. ATD: Automatic transient detection(Read signal length control for Program ROM) to enhance the performance of power consumption at slow mode
27. Package Types: Please refer to the chapter of “PACKAGING INFORMATION” (Left click the link to go to that page)
28. Supported EV board
TM56F1552/22