FEATURES ROM: 4K x 16-bit Flash program memory
2. EEPROM: 256 x 8-bit
3. RAM: 592 x 8-bit
4. STACK: 8 level
5. System clock selection:
Fast-clock:
Internal RC fast clock: Max. 18.432 MHz (can be calibrated)
FXT (external Fast crystal oscillator): 1M~18MHz
Slow-clock
SIRC internal RC slow clock: 50 KHz or 60KHz @VCC=5V
SXT external slow clock: 32.768KHz
6. System clock prescaler:
The system clock can be divided into 1/2/4/8 options
7. Dual system clock:
FIRC+SIRC
FIRC+SXT
FXT+SIRC
8. I/O port: up to 26 programmable I/O pins
Open drain output
CMOS push-pull output
Schmitt trigger input with pull-up resistor options
Support high sink current mode : 70mA @VCC=5V, VOL=0.5V; 140mA@VCC=5V, VOL=1.2V
Support constant current drive mode: 19mA@VCC=5V,VOH=2.5V~3.8V
9. Power Saving Operation Mode
FAST Mode: Slow-clock can be disabled or enabled, Fast-clock keeps CPU running
SLOW Mode: Fast-clock can be disabled or enabled, Slow-clock keeps CPU running
IDLE Mode: Fast-clock and CPU stop. Slow-clock, T2, or Wake-up Timer keep running
STOP Mode: All clocks stop, T2 and Wake-up Timer stop
10. 3 Independent Timers
Timer0
- 8-bit timer divided by 1~256 pre-scaler option, Reload/Interrupt/Stop function
Timer1
- 8-bit timer divided by 1~256 pre-scaler option, Reload/Interrupt/Stop function
- Overflow and Toggle out
T2
- 15-bit timer with 4 interrupt interval time options
- IDLE mode wake-up timer or used as one simple 15-bit time base
- Clock source: Slow-clock (SIRC), Fsys/128
11. Interrupt
Three external interrupt pins
- 1 pin is a falling edge wake-up trigger and interrupt
- 2 pins for rising or falling edge wake-up trigger and interrupt
Timer0 / Timer1 / T2 / WKT Interrupt
ADC Interrupt
TK (2 Touch Key module)
I2C Interrupt
UART Interrupt
All pin interrupts
LVD Interrupt
EEP programming completion interrupt
12. Wake-up timer (WKT)
Clocked by built-in RC oscillator with 4 adjustable interrupt times
20.5 ms/41 ms/82 ms/164 ms @50KHz SRC VCC=3.6V
13. Watchdog Timer (WDT)
Clocked by built-in RC oscillator with 4 adjustable reset times
164ms/328ms/655ms/1311ms @50KHz SRC VCC=3.6V
Watchdog timer can be disabled/enabled in STOP mode
14. PWM
PWM0 :
16 bits, duty-adjustable, period-adjustable controlled PWM
PWM0 clock source: system clock source or FIRC/256 or FIRC or FIRC*2
PWM0 with 4 output modes
Complementary PWM0 output (PWM0P, PWM0N)
Non overlap time durations adjustable. (0~15 PWM CLK)
PWM1~5:
16 bits, duty-adjustable (Independent) , period-adjustable controlled (shared with PWM0)
Clock source (Shared with PWM0)
15. 26 channels, 2 TK module touch keys (TKM0/TKM1)
Each TK module with 13-channel touch keys
Each module include:
3-bit TK reference clock capacitor adjustment
8-bit touch key clock frequency select(can be fixed frequency or auto change)
14-bit TK scan length adjustment
Interrupt/Wake-up CPU while key is pressed
16. I2C Interface
Specific purpose slave I2C interface with interrupt function
17. UART Interface
7/8/9 bits mode TX/RX selectable
Supported Baud-Rate range from 9600bps to 115200 bps with proper selected oscillation frequency and baud rate clock divide
Automatic parity generation and detection
Detects Overrun, Frame Error and Parity Error
18. 12-bit ADC converter with 26 input channels and 1 internal reference voltage
Internal Reference Voltage: VBG 1.18V±1% @VCC=5V~2.5V, 25℃
Internal reference voltage::1/4VCC
ADC reference voltage:VCC, VBG
19. All pin change wake up (negedge and posedge trigger)
20. Reset Sources
Power On Reset/Watchdog Reset/Low Voltage Reset/External Pin Reset
21. Low Voltage Reset (LVR) /Low Voltage Detection Flag (LVD) Option:
16-Level Low Voltage Reset: 1.6~ 3.5 V
16-Level Low Voltage Detection Flag (Disable, 1.7V ~ 3.5V)
22. Operating Voltage:
Fsys= 1 MHz, LVR ~5.5V
Fsys=18.432 MHz, 2.5~5.5V
Note: Power-on VCC must exceed POR 1.6V and selected LVR level, refer to “Electrical Characteristics Graph” to avoid entering ROM dead zone.
23. Operating Temperature Range : -40°C to + 105°C
24. RDCTL: Read signal delay control for Program ROM
The user must switch this register to “4ns” to enhance the performance of minimal operating voltage
25. Integrated 16-bit Cyclic Redundancy Check (CRC)
26. Table Read Instruction: 16-bit ROM data lookup table
27. Instruction set: 43 Instructions
28. Instruction Execution Time
2 system clocks (Fsys) per instruction except branch
29. Built-in 1/2 bias for software LCD display (4 COM)
30. Programming connectivity support 4-wire (ICP) or 5-wire program
31. Package Types:
SOP-28/SSOP-28/TSSOP-20
32. Supported EV board (ICE) on Real Chip Debug
Use PA0/PA1 pin or PC0/PC1 pin
Share with ICP programming pin