TM52F1384

1.	Standard 8051 Instruction set, fast machine cycle
	Executes instructions six times faster than the standard 8051.
2.	Flash Program Memory
	16K Bytes Flash program memory
	Support “In Circuit Programming” (ICP) or “In System Programming” (ISP) for the Flash code
	Code Protection Capability
	BOOT Vector option
	10K erase times at least
	10 years data retention at least
3.	128 Bytes EEPROM Memory
	50K erase times at least
	10 years data retention at least
4.	Total 1280 Bytes SRAM (IRAM + XRAM)
	256 Bytes IRAM in the 8051 internal data memory area
	1024 Bytes XRAM in the 8051 external data memory area (accessed by MOVX Instruction)
5.	Two System Clock type selections
	Fast clock from Internal RC (FRC, 16.588 MHz)
	Slow clock from Internal RC (SRC, 41 KHz)
	System Clock can be divided by 1/2/4/16 option
6.	8051 Standard Timer – Timer0/1/2
	16-bit Timer0, also supports T0O clock output for Buzzer application
	16-bit Timer1, also supports T1O clock output for Buzzer application
	16-bit Timer2, also supports T2O clock output for Buzzer application
7.	24-bit Timer3
	Clock source is Slow clock or FRC/512
	with reload function
	with clear and hold function
8.	UARTs
	UART1, 8051 standard UART, One Wire UART option can be used for ISP or other application
	UART2, the second UART, supports only Mode1 and Mode3
	Additional Baud Rate generator option
 
9.	Seven 16-bit PWMs
【16-bit PWM0 P+N】
	with period-adjustment/buffer-reload/clear and hold function
	Non-overlap durations adjustable
	Half-bridge phase control output
【16-bit PWM1~6】
	share period
	with period-adjustment/buffer-reload/clear and hold function
10.	Master I2C interface (MIIC)
	with MIIC pin select option
Note: SDA/SCL pin select to P3.5/P3.6 or P1.6/P1.7 by MI2CPS (SFR A6h.6)
11.	SPI interface
	Master or Slave mode selectable
	Programmable transmit bit rate
	Serial clock phase and polarity options
	MSB-first or LSB-first selectable
	with SPI pin select option
Note: MSCK/MOSI/MISO pin select to P3.6/P3.5/P3.4 or P2.5/P2.4/P2.3 by SPIPS (SFR A6h.5)
12.	12-bit ADC with 20 channels External Pin Input and 3 channels Internal Reference Voltage
	Internal Reference Voltage: VBG, OPO, 1/4VCC
	ADC reference voltage: VBG / VCC
13.	26-Channel Touch Key (FTK)
	Internal reference key
	With 4 scanning methods
14.	Operational Amplifier
	3 channel input OPP0~2 selectable
	Build-in 4-level OPA gain 1/20/50/100
15.	LCD Controller/Driver
	4Cx20S ~ 8Cx16S selectable
	1/3 Bias
	1/4, 1/5, 1/6, 1/8 Duty
	8-level Brightness selection
 
16.	LED Controller/Driver
	COM with Dead Time
	LED hold option
	8-level Brightness selection
	Brightness uniform / enhancement  option
【Matrix (MX) mode】
	4Cx20S ~ 8Cx16S selectable, Max. 24 pins up to 80~128 dots
【Dot matrix (DMX) mode】
	4Cx4S, 5Cx5S, 6Cx6S, 6Cx7S, 7Cx7S, 7Cx8S, Max. 8 pins up to 56 dots
17.	14 Sources, 4-level priority Interrupt
	Timer0/Timer1/Timer2/Timer3 Interrupt
	INT0/INT1 pin Falling-Edge/Low-Level Interrupt
	INT2 pin Falling-Edge Interrupt
	Port0/1/2/3 Pin Change Interrupt
	UART1 TX/RX Interrupt
	UART2 TX/RX Interrupt
	ADC/Touch Key Interrupt
	MIIC/SPI interrupt
	LVD Interrupt
	PWM0/PWM1 Interrupt
18.	Pin Interrupt can Wake up CPU from Halt/Stop mode
	P3.2/P3.3 (INT0/INT1) Interrupt & Wake-up
	P3.7 (INT2) Interrupt & Wake-up
	Each Port0/1/2/3 pin can be defined as Interrupt & Wake-up pin (by pin change)
Note: Chip cannot enter Halt/Stop mode if INTn pin is low and wakeup is enabled. (INTn=0 and EXn=1, n=0~2)
19.	Max. 26 Programmable I/O pins
	CMOS Output
	Pseudo-Open-Drain, or Open-Drain Output
	Schmitt Trigger Input
	Pin Pull-up can be Enabled or Disabled
	All pin with High sink option (60mA@VCC=5V，VOL=0.1VCC)
20.	Independent RC Oscillating Watch Dog Timer
	400ms/200ms/100ms/50ms selectable WDT timeout options
21.	LDO Regulator for Internal Digital Circuit
 
22.	Five types Reset
	Power on Reset
	Selectable External Pin Reset
	Selectable Watch Dog Reset
	Software Command Reset
	Selectable Low Voltage Reset
23.	16-level Low Voltage Reset (LVR)
	2.05V/2.19V/2.33V/2.47V/2.61V/2.75V/2.89V/3.03V/
3.17V/3.31V/3.45V/3.59V/3.73V/3.87V/4.01V/4.15V (step=0.14V)
24.	16-level Low Voltage Detect (LVD)
	2.05V/2.19V/2.33V/2.47V/2.61V/2.75V/2.89V/3.03V/
3.17V/3.31V/3.45V/3.59V/3.73V/3.87V/4.01V/4.15V (step=0.14V)
	LVD detect polarity option
	LVD Hysteresis 30mV~80mV
25.	Five Power Operation Modes
	Fast/Slow/Idle/Halt/Stop mode
26.	Integrated 16-bit Cyclic Redundancy Check function
27.	Multiplication and Division 
	8 bits Multiplier & Divider (standard 8051)
	16 bits Multiplier & Divider
	32 bits ÷ 16 bits Divider
28.	On-chip Debug/ICE interface
	Use P3.0/P3.1 pin or P2.0/P2.1 pin 
	Share with ICP programming pin
	Mass production writer only supports P3.0/P3.1
29.	Operating Voltage and Current
	VCC = 2.2V ~ 5.5V @FSYSCLK=16.588MHz (-40℃ ~ +105℃)
	ICC = 0.2µA @Stop mode, PWRSAV=1, VCC=3V
	ICC = 2.3µA @Halt mode, PWRSAV=1, VCC=3V
	ICC = 4.1µA @Idle mode, PWRSAV=1, PORPD=1, VCC=3V
30.	Operating Temperature Range
	–40°C ~ +105°C
 
31.	Package Types
	SOP 32-pin (300 mil)
	SOP 28-pin (300 mil)
	SSOP 28-pin (150 mil)