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TM52F0C63

Data Sheet
DS-TM52F0C63_EV093.pdf

8/17/2023
User manual
Development Documnets
AP Notes

Development Tools
T-Link-EV Board
TWR98/TWR99/TWR100/TWR100A

GENERAL DESCRIPTION
TM52 series F0C63 are versions of a new, fast 8051 architecture for an 8-bit microcontroller
single chip with an instruction set fully compatible with industry standard 8051, 
and retains most 8051 peripheral’s functional block. Typically, the TM52 executes
instructions six times faster than the standard 8051 architecture.
The TM52-F0C63 provides improved performance, lower cost and fast time-to-market by
 integrating features on the chip, including 8K Bytes Flash program memory, 
128 Bytes EEPROM, 512 Bytes SRAM, Low Voltage Reset (LVR), Low Voltage Detector (LVD),
 dual clock power saving operation mode, 8051 standard UART and Timer0/1/2, 
real time clock Timer3, 7 set 16-bit PWMs, 19 channels 12-bit A/D Convertor, 
master I2C interface and Watch Dog Timer. It’s a high reliability and low power consumption
 feature can be widely applied in consumer and home appliance products.
BLOCK DIAGRAM


FEATURES
1. Standard 8051 Instruction set, fast machine cycle
 Executes instructions six times faster than the standard 8051.
2. Flash Program Memory
 8K Bytes
 Support “In Circuit Programming” (ICP) or “In System Programming” (ISP) for the Flash code
 Byte Write “In Application Programming” (IAP) mode is convenient as Data EEPROM access
 Code Protection Capability
 10K erase times at least
 10 years data retention at least
*Each IAP address can be programmed more than 10000 times (typical value) .If the customer needs more programming times, a ROM area can be planned to disperse the address written by IAP data. Our company can provide the source code of this usage method.
3. 128 Bytes EEPROM Memory
 30K~50K erase times at least
 10 years data retention at least
4. Total 512 Bytes SRAM (IRAM + XRAM)
 256 Bytes IRAM in the 8051 internal data memory area
 256 Bytes XRAM in the 8051 external data memory area (accessed by MOVX Instruction)
5. Two System Clock type selections
 Fast clock from Internal RC (FRC, 16.588 MHz)
 Slow clock from Internal RC (SRC, 80 KHz)
 System Clock can be divided by 1/2/4/16 option
6. 8051 Standard Timer – Timer0/1/2
 16-bit Timer0, also supports T0O clock output for Buzzer application
 16-bit Timer1, also supports T1O clock output for Buzzer application
 16-bit Timer2, also supports T2O clock output for Buzzer application
7. 15-bit Timer3
 Clock source is Slow clock
 Interrupt period can be clock divided by 32768/16384/8192/65536 option
8. One UART
 8051 standard UART, One Wire UART option can be used for ISP or other application
*Support one UART, pin select to P30/P31 or P02/P16 by TXRXSEL (SFR 93h.7)
9. Seven "16" bits PWMs with prescaler/ period-adjustment
10. One Master I2C interface (MIIC)
*Support one MIIC, pin select to P35/P16 by MSDASEL (SFR B7h.7) , pin select to P13/P02 by MSCLSEL (SFR B7h.6)
11. 12-bit ADC with 19 channels External Pin Input and 3 channels Internal Reference Voltage
 Internal Reference Voltage (VBG): 1.22V±1.5% @VCC=2.5V~5.5V, 25℃
 Internal Reference Voltage: VSS (0V)
 Internal Reference Voltage: VCC/4
 ADC reference voltage selection option: VCC / 2.54V
12. LCD Driver
 Software controlled COM0~3
 1/2 LCD Bias
13. 13 Sources, 4-level priority Interrupt
 Timer0/Timer1/Timer2/Timer3 Interrupt
 INT0/INT1 pin Falling-Edge/Low-Level Interrupt
 INT2 pin Falling-Edge Interrupt
 Port0/1/2/3 Pin Change Interrupt
 UART TX/RX Interrupt
 ADC Interrupt
 Master I2C (MIIC) interrupt
 LVD Interrupt
 PWM0/PWM1 interrupt
14. Pin Interrupt can Wake up CPU from Power-Down (Halt/Stop) mode
 INT0~INT2 Interrupt & Wake-up
 Each Port0/1/2/3 pin can be defined as Interrupt & Wake-up pin (by pin change)
15. Max. 26 Programmable I/O pins
 CMOS Output
 Pseudo-Open-Drain, or Open-Drain Output
 Schmitt Trigger Input
 Pin Pull-up can be Enabled or Disabled
16. Independent RC Oscillating Watch Dog Timer
 400ms/200ms/100ms/50ms selectable WDT timeout options
17. Five types Reset
 Power on Reset
 Selectable External Pin Reset
 Selectable Watch Dog Reset
 Software Command Reset
 Selectable Low Voltage Reset
18. 16-level Low Voltage Reset
 2.25V / 2.40V / 2.55V / 2.70V / 2.80V / 2.95V / 3.10V / 3.25V / 3.40V / 3.55V / 3.70V / 3.85V / 4.0V / 4.15V / 4.30V / 4.45V
19. 15-level Low Voltage Detect
 2.40V / 2.55V / 2.70V / 2.80V / 2.95V / 3.10V / 3.25V / 3.40V / 3.55V / 3.70V / 3.85V / 4.0V / 4.15V / 4.30V / 4.45V
20. Five Power Operation Modes
 Fast/Slow/Idle/Halt/Stop mode
21. Integrated 16-bit Cyclic Redundancy Check function
22. Multiplication and division
 8 bits Multiplier & Divider (standard 8051)
 16 bits Multiplier & Divider
 32 bits ÷ 16 bits Divider
23. On-chip Debug/ICE interface
 Use P3.0/P3.1 pin or P2.0/P2.1 pin
 Share with ICP programming pin
 Mass production writer only supports P3.0/P3.1
24. Operating Voltage and Current
 VCC =2.2V ~ 5.5V @FSYS=16.588 MHz
 ICC =0.1μA @Stop mode, PWRSAV=1, VCC=3V
 ICC =6μA @Halt mode, PWRSAV=1, VCC=3V
 ICC =9μA @Idle mode, PWRSAV=1, LVRPD=0x37, VCC=3V
25. Operating Temperature Range
 –40°C ~ +105°C
26. Package Types
 10-pin MSOP (118 mil)
 16-pin SOP (150 mil)
 20-pin TSSOP (173 mil)
 20-pin SOP (300 mil)
 20-pin QFN (3x3x0.75-0.4mm) (L=0.25mm)
 24-pin SSOP (150 mil)
 28-pin SOP (300 mil)
 28-pin SSOP (150 mil)
 28-pin QFN (4x4x0.75-0.4mm)


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