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TM52eF0C75A

Data Sheet
DS-TM52eF0C86_85_EV091.pdf

3/11/2023
User manual

Development Tools
T-Link-EV Board
TWR98/TWR99/TWR100/TWR100A

GENERAL DESCRIPTION
TM52 series F0C75A are versions of a new, fast 8051 architecture for an 8-bit
microcontroller single chip with an instruction set fully compatible with industry standard
8051, and retains most 8051 peripheral’s functional block. Typically, the TM52 executes
instructions six times faster than the standard 8051 architecture.
The TM52-F0C75A provides improved performance, lower cost and fast time-to-market 
by integrating features on the chip, including 32K Bytes Flash program memory, 1280 Bytes
SRAM, Low Voltage Reset (LVR), Low Voltage Detector (LVD), dual clock power saving
operation mode, 8051 standard UART and Timer0/1/2, real time clock Timer3, LCD/LED
driver, 3 set 16-bit PWMs, 16 channels 12-bit A/D Convertor, 20 channels Touch Key,
I2C/SPI interface and Watch Dog Timer. It’s a high reliability and low power consumption
feature can be widely applied in consumer and home appliance products.
BLOCK DIAGRAM


FEATURES
1. Standard 8051 Instruction set, fast machine cycle
 Executes instructions six times faster than the standard 8051.
2. Flash Program Memory
 32K Bytes
 Support IAP “In Application Programming” (EEPROM like)
 Code Protection Capability
 10K erase times at least
 10 years data retention at least
3. Total 1280 Bytes SRAM (IRAM + XRAM)
 256 Bytes IRAM in the 8051 internal data memory area
 1024 Bytes XRAM in the 8051 external data memory area (accessed by MOVX Instruction)
4. Four System Clock type selections
 Fast clock from 1~18MHz Crystal (FXT)
 Fast clock from Internal RC (FRC, 18.432 MHz)
 Slow clock from 32768Hz Crystal (SXT)
 Slow clock from Internal RC (SRC,80 KHz)
 System Clock can be divided by 1/2/4/16 option
5. 8051 Standard Timer – Timer0/1/2
 16-bit Timer0, also supports T0O clock output for Buzzer application
 16-bit Timer1
 16-bit Timer2, also supports T2O clock output for Buzzer application
6. 15-bit Timer3
 Clock source is Slow clock
 Interrupt period can be clock divided by 32768/16384/8192/128 option
7. UARTs
 UART1, 8051 standard UART
 UART2, the second UART, supports only mode1 and mode3
8. Three independent 16 bits PWMs with period-adjustment
 With PWM0/PWM1/PWM2 Interrupt
9. SPI Interface
 Master or Slave mode selectable
 Programmable transmit bit rate
 Serial clock phase and polarity options
 MSB-first or LSB-first selectable
10. I2C interface (Master / Slave)
11. 20-Channel Touch Key (FTK)
 Internal rFerence key
 With 4 scanning methods
12. 12-bit ADC with 13 channels External Pin Input and 3 channels Internal RFerence Voltage
 Internal RFerence Voltage: VBG 1.22V @VCC=5V~3V, 25℃
 Internal RFerence Voltage: 1/4VCC
 ADC rFerence voltage = 2.5V / VCC
13. LCD Driver
 1/8 duty
 Software controlled COM0~7
 1/2 LCD Bias
14. LED Controller/Driver
 COM with Dead Time
 LED hold option
 Brightness uniform / enhancement option
【Bi-Direction matrix (BiD) mode】
 4C x 6S, Max. 10 pins up to 48 dots
 3groups, 8-level Brightness
【Dot matrix (DMX) mode】
 8C x 8S, Max. 9 pins up to 64 dots
 8-level Brightness
15. 14 Sources, 4-level priority Interrupt
 Timer0/Timer1/Timer2/Timer3 Interrupt
 INT0~INT1 pin low level or falling edge Interrupt
 INT2~INT9 pin Falling-Edge Interrupt
 Port1 Pin Change Interrupt
 UART1/UART2 TX/RX Interrupt
 ADC/Touch Key Interrupt
 SPI Interrupt
 I2C interrupt
 PWM0/PWM1/PWM2 interrupt
16. Pin Interrupt can Wake up CPU from Power-Down (Halt/Stop) mode
 INT0~INT9 Interrupt & Wake-up
 Each Port1 pin can be dFined as Interrupt & Wake-up pin (by pin change)
Note: Chip cannot enter Halt/Stop Mode if INTn pin is low and wakeup is enabled. (INTn=0 and EXn=1, n=0~9)
17. Max. 26 Programmable I/O pins
 CMOS Output
 Pseudo-Open-Drain, or Open-Drain Output
 Schmitt Trigger Input
 Pin Pull-up can be Enabled or Disabled
 All pin with High sink (80mA@VCC=5V,VOL=0.1VCC)
18. Independent RC Oscillating Watch Dog Timer
 400ms/200ms/100ms/50ms selectable WDT timeout options
19. Five types Reset
 Power on Reset
 Selectable External Pin Reset
 Selectable Watch Dog Reset
 Software Command Reset
 Selectable Low Voltage Reset
20. 16-level Low Voltage Detect
 4.3V/4.2V/4.0V/3.9V/3.8V/3.7V/3.6V/3.4V/
3.3V/3.2V/3.1V/3.0V/2.8V/2.7V/2.6V/2.5V
21. 8-level Low Voltage Reset
 4.2V/3.9V/3.7V/3.4V/3.2V/3.0V/2.7V/2.5V
22. Five Power Operation Modes
 Fast/Slow/Idle/Halt/Stop mode
23. Integrated 16-bit Cyclic Redundancy Check function
24. Multiplication and division
 8 bit Multiplier & Divider (standard 8051)
 16 bits Multiplier & Divider
 32 bits ÷ 16 bits hardware Divider
25. On-chip Debug/ICE interface
 Use P3.0/P3.1 pin or P0.0/P0.1 pin
 Share with ICP programming pin


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