FEATURES1. ROM: 8K x 16 bits Flash Program Memory with Page Locker function.
2. EEPROM: 128 x 8 bits
3. RAM: 496 x 8 bits
4. STACK: 8 Levels
5. System Oscillation Sources (Fsys) :
Fast-clock
FIRC (Fast Internal RC) : Max. 18.432 MHz (can be trimmed)
FXT (Fast Crystal): 1M~18MHz
Slow-clock
SIRC (Slow Internal RC) : 50 KHz @VCC=5V
SXT (Slow Crystal): 32.768KHz
6. System Clock Prescaler:
System Oscillation Sources can be divided by 1/2/4/16 as System Clock (Fsys)
7. Dual System Clock:
FIRC+SIRC
FIRC+SXT
FXT+SIRC
8. Power Saving Operation Mode
FAST Mode: Slow-clock can be disabled or enabled, Fast-clock keeps CPU running
SLOW Mode: Fast-clock can be disabled or enabled, Slow-clock keeps CPU running
IDLE Mode: Fast-clock and CPU stop. Slow-clock, T2, or Wake-up Timer keep running
STOP Mode: All clocks stop, T2 and Wake-up Timer stop
9. 3 Independent Timers
Timer0
8-bit timer divided by 1~256 pre-scaler option, Reload/Interrupt/Stop function
Timer1
8-bit timer divided by 1~256 pre-scaler option, Reload/Interrupt/Stop function
Overflow and Toggle out
T2
15-bit timer with 4 interrupt interval time options
IDLE mode wake-up timer or used as one simple 15-bit time base
Clock source: Slow-clock (SIRC), Fsys/128
10. Interrupt
Three External Interrupt pins
1 pin is falling edge wake-up triggered & interrupts
2 pins are rising or falling edge wake-up triggered & interrupt
Timer0/Timer1/T2/WKT (wake-up) Interrupts
ADC Interrupt
TK (3 Touch Key module)
I2C Interrupt
UART Interrupt
Pin Change Interrupt
LVD Interrupt
11. Wake-up (WKT) Timer
Clocked by built-in RC oscillator with 4 adjustable interrupt times
20.5 ms/41 ms/82 ms/164 ms
12. Watchdog Timer
Clocked by built-in RC oscillator with 4 adjustable reset times
164ms/328ms/655ms/1311ms
Watchdog timer can be disabled/enabled in STOP mode
13. PWM
PWM0 :
16 bits, duty-adjustable, period-adjustable controlled PWM
PWM0 Clock source: System clock or FIRC (18.432MHz) or FIRC*2 (36.864MHz)
PWM0 with 4 output modes
Complementary PWM0 output (PWM0P, PWM0N)
Non overlap time durations adjustable. (0~15 PWM CLK)
PWM1~5:
16 bits, duty-adjustable (Independent) , period-adjustable controlled (shared with PWM0)
Clock source (Shared with PWM0)
14. 24-Channel Touch Key with 3 TK-module (TKM0/TKM1/TKM2)
Each TK module with 8-channel touch key
Each module include:
3-bit TK reference clock capacitor adjustment
8-bit touch key clock frequency select(can be fixed frequency or auto change)
14-bit TK scan length adjustment
Interrupt/Wake-up CPU while key is pressed.
15. I2C Interface
Specific purpose slave I2C interface with interrupt function
16. UART Interface
7/8/9 bits mode TX/RX selectable
Supported Baud-Rate range from 9600bps to 115200 bps with proper selected oscillation frequency and baud rate clock divide
Automatic parity generation and detection
Detects Overrun, Frame Error and Parity Error
17. 12-bit ADC Converter with 14 input channels and 1 internal reference voltage
Internal Reference Voltage: VBG 1.20V±1% @VCC=5V~2.5V, 25℃
Internal reference voltage: 1/4VCC
ADC reference voltage: VCC, 2.5V
18. All pin change wake up (negedge and posedge trigger)
19. Reset Sources
Power On Reset/Watchdog Reset/Low Voltage Reset/External Pin Reset
20. Low Voltage Reset (LVR) /Low Voltage Detection Flag (LVD) Option:
16-Level Low Voltage Reset: 2.05 ~ 4.15 V
16-Level Low Voltage Detection Flag (Disable, 2.28V ~ 4.15V)
21. Operating Voltage :
Fsys= 1 MHz, LVR ~5.5V
Fsys=18.432 MHz, 2.5~5.5V
22. Operating Temperature Range : -40°C to + 85°C
23. Integrated 16-bit Cyclic Redundancy Check (CRC)
24. Table Read Instruction: 16-bit ROM data lookup table
25. Instruction set: 39 Instructions
26. Instruction Execution Time
2 system clocks (Fsys) per instruction except branch
27. Built-in 1/2 bias for software LCD display (4 COM)
28. I/O ports: Maximum 26 programmable I/O pins
Open-Drain Output
CMOS Push-Pull Output
Schmitt Trigger Input with pull-up resistor option
29. Programming connectivity support 4-wire (ICP) or 5-wire program
30. Page Locker Size: 512W/640W/768W …./23040W by 128 words step
31. Package Types:
SOP-28
SOP-20
SOP-16
32. Supported EV board (ICE) on Real Chip Debug
Use Pa0/Pa1 pin or PC0/PC1 pin
Share with ICP programming pin