FEATURES1. Low power dissipation.
1.5V/3V operating voltage range.
TM87PL37L 1.5V Power Mode
TM87PL37H 3V Power Mode
2. Powerful instruction set.
Binary addition, subtraction, BCD. BCD can be executed directly in addition, subtraction.
Single-bit manipulation (set, reset, decision for branch).
Various conditional branches.
16 initial working registers and manipulators. (can be extended to all RAM by Page Mode)
Table look-up.
LCD driver data transfer.
3. ROM (MTP) capacity. 15.5K x 16 bits.
Instruction ROM Max. capacity 15.5K x 16 bits.
Program Address X100~X1FFh reversed for Bank Convert Area.
Table ROM Max. capacity 16K x 8 bits.
4. RAM capacity. 2K x 4 bits.
5. With direct/index addressing mode in data RAM access.
6. LCD driver output.
Max 459 LCD dots by 9common outputs and 51 segment outputs.
SEG24~51 can be defined as IOA1~4/CX, RR, RT, RH, IOB1~4/ELC, ELP, BZB, BZ,
IOC/KI1~4, IOD1~4 ,IOE1~4,IOF1~4,IOG1~4 by option.
1/1~1/9 Duty can be selected by option.
1/2 ~1/3 Bias can be selected by option.
Single instruction to turn off all segments.
COM1~9, SEG1~51 can be defined as CMOS or P_open drain type output by option.
COM1~9 pins can be mirrored to COM9~1 by option.
COM2~9/9~2 can be defined as SEG32~39/SEG31~38 by option.
Built-in regulator mode for VL1/2 by option.
7. Input/output ports.
Port IOA 4 pins (with internal pull-low), and can be defined as SEG24~27/CX, RR, RT, RH by option.
Port IOB 4 pins (with internal pull-low), and can be defined as SEG28~31/ELC, ELP, BZB, BZ by option.
Port IOC 4 pins (with internal pull-low, low-level-hold, input signal chattering prevention circuitry), and can be defined as SEG32~35/KI1~4 by option.
Port IOD 4 pins (with internal pull-low, input signal chattering prevention circuitry), and can be defined as SEG36~39 by option.
Port IOE 4 pins (with internal pull-low, input signal chattering prevention circuitry), and can be defined as SEG40~43 by option.
Port IOF 4 pins (with internal pull-low, input signal chattering prevention circuitry), and can be defined as SEG44~47 by option.
Port IOG 4 pins (with internal pull-low, input signal chattering prevention circuitry), and can be defined as SEG48~51 by option.
8. Interrupt function.
External factors 4 (INT pin, Port IOC, IOD & KI input).
Internal factors 4 (Pre-Divider, Timer1, Timer2 & RFC).
9. Built-in EL-light driver.
ELC, ELP. Can be defined as SEG28, 29/IOB1, 2 by option.
10. Built-in Alarm, clock or single tone melody generator.
BZB, BZ. Can be defined as SEG30, 31/IOB3, 4 by option.
11. Built-in resistance to frequency converter.
CX, RR, RT, RH. Can be defined as SEG24~27/IOA1~4 by option.
12. Built-in key matrix scanning function.
KO1~KO16 (Shared with SEG1~16)
KI1~KI4. Can be defined as SEG32~35/IOC1~4 by option.
13. Two 6-bit programmable timers with programmable clock source.
Read out the content in anytime
14. Watchdog timer.
15. Built-in voltage charge halver & pump circuit.
16. Dual clock operation
slow clock oscillation can be defined as X’tal or external RC type oscillator by option.
fast clock oscillation can be defined as 3.58MHz ceramic resonator, internal R or external R type oscillator by option.
17. HALT function.
18. STOP function.
19. Built-in Low Battery Detect.
20. Built-in Low Voltage Reset(2 type).