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TM57P8645

Data Sheet
DS-TM57P8620_25_40_45_EV097.pdf

2023/8/7
User manual

Development Tools
TICE59NB(已停產)
TICE99
TWR98/TWR99/TWR100/TWR100A

BLOCK DIAGRAM



FEATURES
1.	Operating Voltage :
P8620: VBAT= POR~3.6V 
P8625: VBAT= LVCR~1.8V
P8640:VBAT= POR~3.6V 
P8645:VBAT= LVCR~1.8V 
Note: POR means "power on reset" (power on reset), LVCR means "ROM error reset"
Note: VBAT must exceed POR at power-up. Set POROFF = 0x37 (disable POR) to obtain the lowest VBAT operation, LVCR (ROM error reset, follow the minimum operating voltage) is always enabled. Please refer to "POR v.s. SXT32K Min. Operating Voltage" characteristic curve.
2.	Timepiece Current (CPU Off, LCD On, 32K crystal oscillating) :
P8620: 7uA @VDD=3V, VBAT=3V, without power saving
P8620: 3uA @VDD=1.5V, VBAT=3V, with  power saving
P8625: 2uA(1/2bias) or  4uA(1/3bias) @VDD=1.5V, VBAT=1.5V
P8640: 5uA @VDD=3V, VBAT=3V, without power saving
P8640: 3uA @VDD=1.5V, VBAT=3V, with  power saving
P8645: 2uA(1/2bias) or  4uA(1/3bias) @VDD=1.5V, VBAT=1.5V
3.	Program ROM: 
P8620: 2K x 14 bit OTP
P8625: 2K x 14 bit OTP
P8640: 4K x 14 bit OTP
P8645: 4K x 14 bit OTP
4.	RAM: 
P8620: 176 bytes
P8625: 176 bytes
P8640: 336 bytes
P8645: 336 bytes
5.	STACK: 6 Levels
6.	System Oscillation Sources (Fsys) :
	Fast-clock
-	FIRC (Fast Internal RC) : 2.7MHz @VDD=3V; 0.9MHz @VDD=1.5V
	Slow-clock
-	SIRC (Slow Internal RC) : 36KHz @VDD=3V; 32.768KHz @VDD=1.5V
-	SXT (Slow Crystal) : 32768 Hz
	System Oscillation Sources can be divided by 1/2/4/8 as System Clock (Fsys)
	Dual System Clock Switching between Fast-clock and Slow-clock
-	FIRC + SIRC
-	FIRC + SXT
7.	Power Saving Operation Mode
	FAST Mode: CPU running at Fast-clock
	SLOW Mode: CPU running at Slow-clock
	IDLE Mode: Fast-clock and CPU stop; Slow-clock, Timer2 and LCD keep running
	STOP Mode: All clocks stop
8.	Resistance to Frequency Converter (RFC)
9.	Three Independent Timers
	Timer0 (TM0)
-	8-bit timer with divided by 1~256 pre-scale option, counter/reload/interrupt/stop/capture function
-	Clock sources: Fsys or Slow-clock (SIRC/SXT)    /1/4/16/64
	Timer1 (TM1)
-	8-bit timer with divided by 1~256 pre-scale option, reload/interrupt/stop/capture/clear function
-	Clock source: Fsys
	Timer2 (T2)
-	21-bit timer with 4 interrupt time period options (60s/1s/0.5s/0.125s)
-	Clock sources: Fsys /128 or Slow-clock (SIRC/SXT)
-	IDLE mode wake-up, if clock source is Slow-clock
10.	Interrupts
	Three External Interrupt pins (INT0~INT2)
-	Rising or falling edge triggered interrupt
	Timer0/Timer1/Timer2 Interrupts
	PWM0 Interrupt
	RFC overflow Interrupt
	LBD overflow Interrupt
11.	Wake up
	External Interrupt pins (INT0~INT2) can wake up CPU in IDLE/STOP mode.
	PB [7:0] low-level can wake up CPU in IDLE/STOP mode.
	Timer2 Interrupt can wake up CPU in IDLE mode if Timer2 clock source is Slow-clock.
	PWM0 Interrupt can wake up CPU in IDLE mode if PWM0 clock source is Slow-clock.
12.	LCD Controller / Driver
	Four LCD brightness adjustable  (only use in 1/3 bias)
	1/3 duty or 1/4 duty option
-	P8620:
MAX: 12 SEG x 4 COM,
 1/3 LCD Biasvoltage, typical value is VL1=1.0V, VL2=2.0V, 和 VLCD=3.0V
-	P8625:
MAX: 10 SEG x 4COM,
1/3 LCD Bias voltage, typical value is VL1=1.0V, VL2=2.0V, and VLCD=3.0V
1/2 LCD Bias voltage, typical value is VL1=1.5V 和 VLCD=3.0V
-	P8640:
MAX: 28 SEG x 4 COM,
1/3 LCD Biass voltage, typical value is VL1=1.0V, VL2=2.0V, and VLCD=3.0V
-	P8645:
MAX: 26 SEG x 4 COM,
1/3 LCD Bias voltage, typical value is VL1=1.0V, VL2=2.0V, and VLCD=3.0V
1/2 LCD Bias voltage, typical value is VL1=1.5V 和 VLCD=3.0V
13.	Watchdog Timer (WDT)
	Clocked by system clock with 2 adjustable reset times, 216/Fsys or 215/Fsys
-	1.8sec/0.9sec @VDD=3V (Fsys = SIRC) 
-	2.0sec/1.0sec @VDD=1.5V (Fsys = SIRC) 
	Watchdog timer is disabled in IDLE/STOP mode 
14.	 Two 8-bit PWMs for Buzzer / IR application (PWM0&PWM1)
	Adjustable Period & Clock Pre-scale
	Clock sources: Fast-clock or Slow-clock
	PWM0 output amplitude can be doubled (only for P8625 and P8645)
15.	Four types Reset
	Power On Reset/Low Voltage Reset (POR)
P8620:1.6V@25°C
P8625:1.1V@25°C
P8640:1.6V@25°C,
P8645:1.1V@25°C
	ROM check Reset (LVCR)
 Follow the minimum operating voltage and always enable.
	External Pin Reset (INT0~INT2)
	Watchdog Reset (WDT)
16.	Low Battery Detector (LBD) by BandGap Voltage Reference
P8620: Detect VBAT from 2.4V to 3.0V
P8625: Detect VBAT from 1.2V to 1.5V @LCDON=1
P8640: Detect VBAT from 2.4V to 3.0V
P8645: Detect VBAT from 1.2V to 1.5V @LCDON=1
17.	Operating Temperature Range :
P8620: -40°C to + 85°C
P8625: -40°C to + 85°C
P8640: -40°C to + 85°C
P8645: -40°C to + 85°C
18.	Package Type : 
P8620: Dice-form / SOP28
P8625: Dice-form / SOP28
P8640: Dice-form / SSOP48 / LQFP48
P8645: Dice-form / SSOP48 / LQFP48
19.	Supported EV board on ICE
EV board: EV8228
EV8228 does not support the interrupt of low battery detection (LBD), RFC1T architecture, HIX2 function and IAP function.


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