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TM52F8558

Data Sheet
DS-TM52F8558_EV093.pdf

7/19/2022
User manual

Development Tools
T-Link-EV Board
TWR98/TWR99/TWR100/TWR100A

BLOCK DIAGRAM


FEATURES
1.	Standard 8051 Instruction set, fast machine cycle
	Executes instructions six times faster than standard 8051
2.	8K Bytes Flash Program Memory
	Support “In Circuit Programming” (ICP) for the Flash code
	Code Protection Capability
	10K erase times at least
	10 years data retention at least
3.	128 Bytes EEPROM Memory
	50K erase times at least
	10 years data retention at least
4.	Total 512 Bytes SRAM (IRAM+XRAM)
	256 Bytes IRAM in the 8051 internal data memory area
	256 Bytes XRAM in the 8051 external data memory area (accessed by MOVX Instruction)
5.	Two System Clock type Selections
	Fast clock from Internal RC (FRC, 16.5888 MHz)
	Slow clock from Internal RC (SRC, 80 KHz)
	System clock can be divided by 1/2/4/16 option
6.	8051 Standard Timer – Timer0/1/2
	16-bit Timer0, also supports T0O clock output for Buzzer application
	16-bit Timer1, also supports T1O clock output for Buzzer application
	16-bit Timer2, also supports T2O clock output for Buzzer application
7.	15-bit Time3
	Clock source is Slow clock or FRC/512
	Interrupt period can be clock divided by 32768/16384/8192/128 option
8.	8051 Standard UART
	One Wire UART option
9.	Two independent 16 bits PWMs with period-adjustment/buffer-reload/clear and hold function
10.	One Master I2C Interface
11.	12-bit ADC with 12 Channels External Pin Input, 2 Channels Internal Reference Voltage and 1 OPA Output Voltage
12.	Build-In OP Amp x 1 for the IGBT Current Sensing
	Low Power Rail-to-Rail Input / Output
	Vos < |2mV| by calibration
	High Gain-Bandwidth 2.1MHz
	High Open Loop Gain 90dB
	CMRR 80dB, PSRR 80dB
13.	Build-In Voltage Comparator x 5 for IH Cooker Application
	Vos < |2mV| by calibration
	|40mV| Hysteresis Option (Disable / Enable)
	Phase Protect Detector (PPD)
14.	One 9-Bit Programmable Pulse Generator (PPG) Output Channel
	Sing Pulse Mode / Synchronous Mode
	Direct / Approach Reload Mode
	Programmable Output Delay Time (Synchronous Mode only)
	Auto-Decrement Pulse Width Control
	Over-Voltage / Over-Current Protection
15.	Multiplication and division 
	8 bits Multiplier & Divider (standard 8051)
	16 bits Multiplier & Divider
	32 bits ÷ 16 bits hardware Divider
16.	Integrated 16-bit Cyclic Redundancy Check function
17.	20 Sources, 4-level Priority Interrupt
	Timer0/Timer1/Timer2/Timer3 Interrupt
	INT0/INT1 Falling-Edge/Low-Level Interrupt
	Port1 Pin Change Interrupt
	UART TX/RX Interrupt
	P3.7 (INT2) Interrupt
	ADC Interrupt
	I2C Interrupt
	PPG/PPD Interrupt
	CMP1~5 Interrupt
	PWM0/PWM1 Interrupt
18.	Pin Interrupt can Wake up CPU from Power-Down (Stop) mode
	P3.2/P3.3 (INT0/INT1) Interrupt & Wake-up
	P3.7 (INT2) Interrupt & Wake-up
	Each Port1 pin can be defined as Interrupt & Wake-up pin (by pin change)
19.	Max. 17 Programmable I/O pins
	CMOS Output
	Pseudo-Open-Drain, or Open-Drain Output
	Schmitt Trigger Input
	Pin Pull-up can be Enable or Disable
20.	Independent RC Oscillating Watchdog Timer
	400ms/200ms/100ms/50ms Selectable WDT Timeout options
21.	Five types Reset
	Power on Reset
	Selectable External Pin Reset
	Software Command Reset
	Selectable Watchdog Timer Reset
	Selectable Low Voltage Reset
22.	4-level Low Voltage Reset
	2.7V/3.2V/3.8V/4.3V
23.	Four Power Saving Operation Modes
	Fast/Slow/Idle/Stop Mode
24.	On-chip Debug/ICE interface
	Use P3.0/P3.1 pin
	Share with ICP programming pin
25.	Operating Voltage and Current
	VCC=3.7V ~ 5.5V @FSYSCLK=16.5888 MHz
	VCC=2.5V ~ 5.5V @FSYSCLK=8.2944 MHz
	ICC=52µA @Stop mode, LVR enable, PWRSAV=0, VCC=5V
	ICC=47µA @Stop mode, LVR enable, PWRSAV=0, VCC=3V
	ICC<0.1µA @Stop mode, LVR disable, PWRSAV=1, VCC=5V
26.	Operating Temperature Range
	–40*C ~ +85*C
27.	Package Types
	SOP 20-pin (300 mil)
	QFN 20-pin (3*3*0.75-0.4mm)
	SOP 16-pin (150 mil)


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