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TMU3131F8

Data Sheet
DS-TMU3131F8_EV091.pdf

2021/2/2
User manual

Development Tools
TICE59NB(已停產)
TICE99
T-Link-EV Board

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BLOCK DIAGRAM


FEATURES
RISC CPU:
	Only 37 instructions 
	Instruction Execution Time
2-cycle instructions except branch
	Operating clock
	Fast Clock:
-	In USB mode IRC 48 MHz +/-0.25%
-	CPU Clock control:
	12 MHz / 6 MHz / 3 MHz / 1.5 MHz
	Clock Output:
-	6 MHz / 12 MHz Output
	8Kx14 internal flash Program Memory
	Memory
	160 bytes on F-plane
	128 bytes on R-plane
	8 bytes *5 on R-plane
	8-level Stack
	Interrupt 
	16 kinds of interrupt vector
-	 USB EP0 SET0 Receive Interrupt
-	USB EP0 OUT Receive Interrupt
-	USB EP0 Transmit Interrupt
-	USB EP1 Transmit Interrupt
-	USB EP2 Transmit Interrupt
-	USB Suspend Interrupt
-	USB EP3 Bulk Transmit Interrupt
-	USB EP4 Bulk Transmit Interrupt
-	USB Bus Reset Interrupt
-	USB Resume Interrupt
-	Wake-up Timer Interrupt
-	Timer0 Interrupt
-	PB0 External I/O Interrupt
-	VDD5V Rise interrupt
-	Timer1 Interrupt
	Automatic Store/Restore W and STATUS 

Power Features 
	Operation Voltage 
	Low Voltage Reset Voltage to 5.5V
	Maximum Operation range 2.1V to 5.5V
Built-in 3.3V Regulator covers 3.3 to 5.5V
	Chip Operating Voltage range 2.1 to 3.6V		Operation Current 
     USB mode (Internal 3.3V Regulator used)
	Normal mode 
-	5V@ 12 MHz, 4.1 mA typical
-	5V@ 6 MHz, 2.8 mA typical
-	5V@ 3 MHz, 2.3 mA typical
-	5V@ 1.5 MHz, 1.8 mA typical
	Suspend mode
-	5V@ 12 MHz, 360 uA typical
	Power down mode
-	5V@  1 uA typical 
	H/W Reset
	External active low reset (RSTN)
	Built-in Power-On Reset (POR)
	Low Voltage Reset - 2.1V (LVR)
	Watchdog Reset (WDT)

Peripheral Features
	I/O Port:
	Maximum 17 programmable I/O pins
	Pseudo-Open-Drain Output (P.O.D.)
	Open-Drain Output (O.D.)
	CMOS Push-Pull Output (P.P.)
	Schmitt Trigger Input

	Timers
	Timer0 is 8-bit with 8-bit prescaler, Counter/Capture/Interrupt function
	Timer1 is 8-bit with Capture / Reload / Interrupt function
	PWM
	Built-in 8-bit PWM generator
	PWM0 with prescaler / period  adjustment / buffer-reload / rising-falling output
	Watchdog Timer
	Clocked by on-chip oscillator with 4 adjustable Reset/Interrupt time durations (112 ms / 56 ms / 28 ms / 14 ms)
	Wake-up Timer (896 ms / 448 ms / 224 ms / 112 ms)
	SPI Interface
	 Master only
	Programmable transmit bit rate
	Serial clock phase and polarity options
	MSB-first or LSB-first selectable


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