FEATURES1. ROM: 1K x 14 bits OTP or 512 x 14 bits TTP™ (Two Time Programmable ROM)
2. RAM: 48 x 8 bits
3. STACK: 5 Levels
4. I/O ports: Two Bit programmable I/O ports (Max. 12 pins)
5. Two Independent Timers
※8-bit timer0 with divided by 1~256 pre-scale option, counter function, Stop counting
※15-bit timer2 with 4 interrupt interval option
Timer2 is used to idle mode wake-up timer or one simple 15-bit time base
6. One 8-bit PWM with presale/period-adjustment/buffer-reload/clear and hold function
7. Operation Voltage and Speed : VDD=1.5V, @6MHz; VDD=1.1V, @SIRC Mode
8. PA1~PA6, PB1~PB3 individual pin low level wake up
9. Oscillation Sources
※Fast Clock:
- FXT (Fast Crystal): 1M~24MHz
- FIRC (Fast Internal RC): 4/8MHz
- XRC (External R, External C):10K~3MHz
※Slow Clock:
- SXT (Slow Crystal): 32768Hz
- XRC (External R, External C):10K~3MHz
- SIRC (Slow Internal RC): 168K/40K/9.8K/2.6KHz, @5V; 128K/30.3K/7.6K/2K, @3V
10. Power Saving Operation Mode
- Fast Mode: Slow Clock can be disabled or enabled
- Slow Mode: Fast Clock stops, CPU running
- Idle Mode: Slow Clock running, CPU stops, Timer2 is running
- Stop Mode: All Clocks stop, Wake-up Timer disable or enable
11. Dual System Clock
- FIRC + SIRC
- FIRC + SXT
- FIRC + XRC
- FXT + SIRC
- XRC + SIRC
Reset: Power On Reset, Watchdog Reset, Low Voltage Reset, External pin Reset
12. 2-Level Low Voltage Reset : 1.5V/2.3V (Can be disabled)
13. Operation Voltage: Low Voltage Reset Level to 5.5V
14. Interrupt
※Three External Interrupt pins:
- Two pins are falling edge triggered
- One pin is rising or falling edge triggered
※Timer0, Timer2, Wake-up Timer Interrupt
※PWM0 interrupt
15. Watchdog Timer
※Clocked by built-in RC oscillator with 4 adjustable Reset/Interrupt Time
(106ms/52ms/27ms/13ms, @5V; 139ms/68ms/35ms/17ms, @3V)
※Watchdog timer can be disabled/enabled in STOP mode
16. I/O Ports
※CMOS Output
※Pseudo-Open-Drain or Open-Drain Output
※Schmitt Trigger Input with/without pull-up resistor
17. Instruction set: 36 Instructions
18. Package Types: 14 DIP/SOP