;*************************************************************
;*********************TM57FLA80*******************************
;*************************************************************
;*************************************************************
;;;F plane register define
;*************************************************************
;*************************************************************
INDF		EQU	00H		;Indirect addressing register
TIMER0		EQU	01H		;Timer0 content
PC		EQU	02H		;Program counter
STATUS		EQU	03H		;Status register
;*************************************************************
ROMPAGE			EQU	7	;program rom page select
GBIT			EQU	6	;general purpose bit
RAMBANK			EQU	5	;RAM bank selection
TO			EQU	4	;WDT time out flag
PD			EQU	3	;Sleep mode flag
Z			EQU	2	;Zero Flag
DC			EQU	1	;Decimal Carry Flag
C			EQU	0	;Carry Flag
;*************************************************************
FSR		EQU	04H		;File select register
PAD		EQU	05H		;PortA pin or "data register"
PBD		EQU	06H		;PortB pin or "data register"
RSR		EQU	07H		;R-Piane file select register
INTE1		EQU	08H		;interrupt enable group 1, 1=enable 0=disable
;*************************************************************
PWM0IE			EQU	7	;pwm0 interrupt enable
TM2IE			EQU	6	;timer2 interrupt enable
TM1IE			EQU	5	;timer1	interrupt enable
TM0IE			EQU	4	;timer0 interrupt enable
WKTIE			EQU	3	;wakeup timer interrupt enable
XINT2E			EQU	2	;xint2(PB1)failling interrupt enable
XINT1E			EQU	1	;xint1(PB0)failling interrupt enable
XINT0E			EQU	0	;xint0(PA0)failling interrupt enable
;*************************************************************
INTF1		EQU	09H		;Interrupt flag register group1
;*************************************************************
PWM0F			EQU	7	;pwm0 interrupt event pending flag,set by h/w while pwm0 overflow
TM2F			EQU	6	;timer2 interrupt event pending flag,set by h/w while timer2 match
TM1F			EQU	5	;timer1	interrupt event pending flag,set by h/w while timer1 overflow
TM0F			EQU	4	;timer0 interrupt event pending flag,set by h/w while timer0 overflow
WKTF			EQU	3	;wakeup timer interrupt event pending flag,set by h/w while pwakeup timer timeout
XINT2F			EQU	2	;xint2(PB1) pin failling interrupt event pending flag
XINT1F			EQU	1	;xint1(PB0) pin failling interrupt event pending flag
XINT0F			EQU	0	;xint0(PA0) pin failling interrupt event pending flag
;*************************************************************
TIMER1L		EQU	0AH		;timer1 content low btye
;*************************************************************
TIMER1H		EQU	0BH		;timer1 content high btye
;*************************************************************
PWM0DUTY	EQU	0CH		;PWM0 duty 8-bit
TM1CTRL		EQU	0DH		;timer1 count register
;*************************************************************
CLRTM1			EQU	3	;timer1 clear and hold when this bit is 1
CLRPWM0			EQU	2	;pwm0 clear and hold when this bit is 1
STOPTM1			EQU	1	;stop timer1 when this bit is 1
STOPTM0			EQU	0	;stop timer0 when this bit is 1
;*************************************************************
INTE2		EQU	0EH		;interrupt enable group 2, 1=enable 0=disable
;*************************************************************
URTIE			EQU	6	;uart tx/rx complete interrupt enable
SPIIE			EQU	5	;spi tx/rx complete interrupt enable
XINT7E			EQU	4	;xint7(PA1) interrupt enable
XINT6E			EQU	3	;xint6(PB7) interrupt enable
XINT5E			EQU	2	;xint5(PB6) interrupt enable
XINT4E			EQU	1	;xint4(PB3)failling interrupt enable
XINT3E			EQU	0	;xint3(PB2)failling interrupt enable
;*************************************************************
INTF2		EQU	0FH		;Interrupt flag register group2
;*************************************************************
URTIIF			EQU	6	;uart interrupt event pending flag,set by h/w while pwm0 overflow
SPIIIF			EQU	5	;spi interrupt event pending flag,set by h/w while timer2 match
XINT7IF			EQU	4	;xint7(PA1) pin failling interrupt event pending flag
XINT6IF			EQU	3	;xint6(PB7) pin failling interrupt event pending flag
XINT5IF			EQU	2	;xint5(PB6) pin failling interrupt event pending flag
XINT4IF			EQU	1	;xint4(PB3) pin failling interrupt event pending flag
XINT3IF			EQU	0	;xint3(PB2) pin failling interrupt event pending flag
;*************************************************************
ADCDATAH	EQU	10H		;ADC conversion result MSB
ADCDATAL	EQU	11H		;ADC conversion result LSB(BIT7~4)
;*************************************************************
ADCSELECT	EQU	11H		;ADC conversion result and selectchannel register 
ADCSTART		equ	3	;H/W clear this bit after adc end of conversion
					;S/W set this bit to start adc conversion
					;bit2~0 ADC channel select0:ADC0...7:ADC7
;*************************************************************
PDD		EQU	12H		;PortD pin or "data register"
PED		EQU	13H		;PortE pin or "data register"
PFD		EQU	14H		;PortF pin or "data register"
PGD		EQU	15H		;PortG pin or "data register"
PWM1DUTY	EQU	16H		;pwm1 duty 8 bit
UARTC		EQU	17H		;uart conterol register
;*************************************************************
URTD9			EQU	7	;transmitted 9th bit
					;bit6~5 uart mode select.00 :7 bit 01:8bit 10:9bit 11:reserved
					;bit4 reserved  
TXE			EQU	3	;transmission. 0:disable  1:enable
RXE			EQU	2	;packet reception. 0:disable 1:enable
UARTE			EQU	1	;1:uart func enable   0:uart func disable
UINVEN			EQU	0	;1:enable tx/rx output/input inversion  0:disable inversion
;*************************************************************
UARTS		EQU	18H		;uart status register.even and rpe are control bits
;*************************************************************
UTBE			EQU	7	;1:tx buffer empty  0:tx is transmitting
URRD9			EQU	6	;1:received 9th bit
EVEN			EQU	5	;1:even 0:odd parity (both tx and rx)
PRE			EQU	4	;1:enable 0:disable parity addition (both tx and rx)
PRERR			EQU	3	;set  to 1 when parity error occurs,clear to 0 by f/w
OVERR			EQU	2	;set  to 1 when overrun error occurs,clear to 0 by f/w
FMERR			EQU	1	;set  to 1 when frame error occurs,clear to 0 by f/w
URBF			EQU	0	;set to 1 when 1 byte(or 9 bits) is received.read urrd will clear to 0 automatically 
					;and then to receive the succeeding data without overrun error.
;*************************************************************
URDATA		EQU	19H		;uart transmission/reception data buffer
SPID		EQU	1AH		;SPI transmission/reception data buffer
SPIS		EQU	1BH		;spi status register
;*************************************************************
RCVERR			EQU	7	;set to 1 when spi slave receices error,clear to 0 by f/w
RCVBF			EQU	6	;h/w set to 1 when spi receives buffer is full .f/w read spid willclear to 0 auto matically
TXBEPY			EQU	5	;set to 1 shen spi transmitted buffed is empty,writing spid will clear to 0 and start 
					;transmiting or wait for master's clock and data
WCOL			EQU	4	;exchange 0:on waite collision occurs
;*************************************************************
;*************************************************************
;*************************************************************
;;;R plane register define
;*************************************************************
;*************************************************************
OPTION		EQU	02H		;
;*************************************************************
CAPOLARITY		EQU	7	;timer0 capture polarity.0;high level capture  0:low level capture
T0CAPTURE		EQU	6	;1:timer0 works in capture mode ;0:timer0 works in counter mode
T0IEDGE			EQU	5	;T0I(PA2) rising(0)/falling(1) edge to increase timer0/psc count
SELT0I			EQU	4	;Timer/psc clock source is intstuction cycle(0) /T0I pin(1)
					;TM0PSC(Bit3~Bit0)
                              		;0000:Timer1 clock is "TIMER0 input clock" divide by 1
                             		;0001:Timer1 clock is "TIMER0 input clock" divide by 2
                             		;~~~
					;0111:Timer1 clock is "TIMER0 input clock" divide by 128
					;1000:Timer1 clock is "TIMER0 input clock" divide by 256
;*************************************************************
PWRDOWN		EQU	03H		;Power-down mode register,writer this register to enter power down moe
CLRWDT		EQU	04H		;WDT/WKT control register,writer this register to clear WDT/WKT
PAE		EQU	05H		;PortA control register,each bit control its corresponding PIN (0:INPUT   1:OUTPUT)
PBE		EQU	06H		;PortB control register,each bit control its corresponding PIN (0:INPUT   1:OUTPUT)
PWM0PRD		EQU	07H		;pwm0 period
PAPU		EQU	08H		;PortA(Bit6~Bit0) pull up register,"0" for PullUp resistor is Enable,"1" for Disable
PBPU		EQU	09H		;PortB(Bit1~Bit0) pull up register,"0" for PullUp resistor is Enable,"1" for Disable
LCD_PU		EQU	0Ah		;Miscellaneous register
;*************************************************************
					;bit6~4 lcd pin select
					;000 0pin all is i/o
					;001 8pin com[0~3],seg[20~23]lcd,PED,PFD,PGD is i/o
					;010 12pin com[0~7],seg[16~19]lcd,PED[3~0],PFD,PGD is i/o
					;011 16pin com[0~7],seg[8~19]lcd,PFD,PGD is i/o
					;100 20pin com[0~7],seg[4~19]lcd,PFD[3~0],PGD is i/o
					;101 24pin com[0~7],seg[4~19]lcd,PGD is i/o
					;110 26pin com[0~7],seg[2~19]lcd,PGD[3~2] is i/o
					;111 28pin com[0~7],seg[0~19]lcd,all lcd
PGPU			EQU	3	;PG pull-up   0=enable   1=disable
PFPU			EQU	2	;PF pull-up   0=enable   1=disable
PEPU			EQU	1	;PE pull-up   0=enable   1=disable
PDPU			EQU	0	;PDD pull-up   0=enable   1=disable
;*************************************************************
WCP_PSC		EQU	0Bh		;Miscellaneous register
;*************************************************************
CPUCLKO			EQU	7	;1=cpuclk output to PB2 pin  0=PB2 is general i/o if pwm1e=0
PWM0PE			EQU	6	;1=pwm0 positive output to PB1 pin 0=PB1 is general i/o
PWM0NE			EQU	5	;1=pwm0 negative output to PB0 pin 0=PB0 is general i/o
PWM1E			EQU	4	;1=pwm1 output to PB2 pin  0=PB2 is genral i/o pin if cpuclk=0
SYNCLKO			EQU	3	;1=instruction clock(fose/2) output to PA3 if PAE[3]=1 and not fxt mode
T1OUT			EQU	2	;1=T1OUT to PB3 pin  0=PB3 as general i/o
					;WKTPSC bit1~0     wdt/wkt period 
					;00	20ms
					;01	40ms
					;10	80ms
					;11	160ms
;*************************************************************
A_T_P_PSC	EQU	0cH		;Miscellaneous register
;*************************************************************
					;bit6~4 adc clock frequency selection
					;000	Fosc/256
					;001	Fosc/128
					;010	Fosc/64
					;011	Fosc/32
					;100	Fosc/16
					;101	Fosc/8
					;110	Fosc/4
					;111	Fosc/2
					;bit3~2 pwm0psc(pre-scale)	
					;00	Fosc
					;01	Fosc/2
					;10	Fosc/4
					;11	Fosc/8
T1CAPTURE		EQU	1	;1=timer1 working in capture mode timer1 measure CAPT period
TM1PSC			EQU	0	;timer1 clock select. 1=Fosc   0=Fosc/2
;*************************************************************
TM2CTRL		EQU	0DH		;
;*************************************************************
INT6EDGE		EQU	6	;0=int6 pin failling interrupt;1=int6 pin rising interrupt
INT0EDGE		EQU	5	;0=int0 pin failling interrupt;1=int0 pin rising interrupt
TIMER2CLK		EQU	4	;0=timer2 clock is sub clock;  1=timer2 clock is Fosc/128
					;bit3~2 TIMER2DIV(timer interrupt is timer2 clock divide by)
					;00	32768
					;01	16384
					;10	8192
					;11	128
					;bit1~0 LCDCLK(LCDCLK is timer2 clock divide by)
					;00	128
					;01	64
					;10	32
					;11	16
;*************************************************************
TKCTRL		EQU	0EH		;
;*************************************************************
TKE			EQU	6	;1=touch key enable	0=touch key disable
					;bit5~4 TKSPEED(touch key Oscillation Frequency Select)
					;00	Fasttest touch key clock
					;11	Slowest touch key clock
					;bit3~0	TKSEL(touch key channel select)
					;0000	TK0
					;0001	TK1
					;......
					;1111	TK15
;*************************************************************
TESTREG		EQU	0FH		;test register
CLKCTRL		EQU	10H
;*************************************************************
ATOSAVE			EQU	4	;auto save W register and STATUS register when interrupt and restore them when exit form  interrupt
STOPFCK			EQU	3	;1=stop fast XTAL/FXRC oscillator 0=enable fast oscillator
SUBCKE			EQU	2	;1=enable slow XTAL/XRC oscilltor 0= disable
SUBXTC			EQU	1	;1=sub clock is slow XRC  0=sub clock is slow XTAL	
SELSUB			EQU	0	;1=select sub clock as cpu clock  0=fast clock as cpu clock
;*************************************************************
LCDCTRL		EQU	11H		;
;*************************************************************
LCDON			EQU	7	;1=LCD enable 0=disable
					;bit6~5 LCDDUTY
					;00	static
					;01	1/3duty
					;10	1/4duty
					;11	1/8duty
					;bit4~3 LCDBIAS(lcd bias
					;00	1/2bias
					;01	1/3bias
					;1x	1/4bias
					;bit2~0 LCDBRIT(lcd brightness)
					;000	most darkness
					;111	most brightness
;*************************************************************
PDE		EQU	12H		;PortD control register,each bit control its corresponding PIN (0:INPUT   1:OUTPUT)
PEE		EQU	13H		;PortE control register,each bit control its corresponding PIN (0:INPUT   1:OUTPUT)
PFE		EQU	14H		;PortF control register,each bit control its corresponding PIN (0:INPUT   1:OUTPUT)
PGE		EQU	15H		;PortG control register,each bit control its corresponding PIN (0:INPUT   1:OUTPUT)
ADPIN		EQU	16H		;0=select adc pin type,1=select i/o pin type
UBAUD		EQU	17H		;uart baudrate divisor
SPIBR		EQU	18H		;
;*************************************************************
					;bit6~4 SPPR(SPI baud rate prescaler divisor
					;000	divided by 1
					;001	divided by 2
					;~~~~
					;110	divided by 7
					;111	divided by 8
					;bit2~0 SPR(spi baud rate divisor
					;000	divided by 2
					;001	divided by 4
					;~~~~
					;110	divided by 128
					;111	divided by 256
;*************************************************************
SPICR		EQU	19H		;
;*************************************************************
MSTR			EQU	5	;1=spi as master  0=spi as slave
CPOL			EQU	4	;clock polarity 1=active-low spi clock(idles high) 0=active-high spi clock(idles low)
CPHA			EQU	3	;clock phase 1=first edge of sck occurs at the begin of data  0=first edge of occurs at the middle of data
SSOE			EQU	2	;SS output enable  1=enable  0=disable
LSBFE			EQU	1	;LSB first enable  1=LSB first 0=MSB first
SPE			EQU	0	;1=spi enable  0=spi disable
;*************************************************************
IVC_REG		EQU	1Ah		;regulator control in stop mode
;*************************************************************
;LCDRAM 0X20~~X033   			;lcd ram initial values are not define
;*************************************************************
W		EQU		0
F		EQU		1			 